1. Field of the Invention
The present invention relates generally to testing integrated circuits. More particularly, the present invention relates to testing integrated circuit memory using error-correction code (ECC) bits.
2. Background Information
Memory yield is a major factor in chip yield. Memory consumes half of the total chip area of today's average semiconductor, and this fraction is projected to rise dramatically in coming years. Accordingly, it is highly desirable to increase memory yield.
One conventional approach to increasing memory yield is laser repair. According to this approach, each chip includes extra memory elements such as rows, columns, and banks, which be connected by burning on-chip fuses using laser light to replace any defective memory elements found during memory test.
Another conventional approach is to accept a small number of memory defects, and to correct the data as it is read from the defective memory cells using an error-correction scheme. Conventional error-correction codes (ECC) are used to generate error-correction (EC) bits as data is written to memory. The EC bits are then used to correct the data as it is read from the memory if the number of data errors is equal to, or less than, the power of the code. Some codes can also detect errors when the number of errors is too great to correct. For example, single-error correct, double-error detect (SECDED) codes can be used to correct a one-bit error in a word of data, and to detect a two-bit error in a data word. In this specification, both types of codes are referred to as error-correction (EC) codes. The benefits of such schemes are disclosed in U.S. Non-Provisional patent application Ser. No. 10/184,334 filed Jun. 26, 2002, the disclosure thereof incorporated by reference herein in its entirety.
FIG. 1 shows a test system 100 for a conventional integrated circuit (IC) 102 using an EC code. Test system 100 comprises an IC 102 and a tester 104. IC 102 comprises a memory 106 comprising a plurality of memory lines 120A through 120N. Each memory line 120 comprises a plurality of data cells 122 each adapted to store a bit of data and a plurality of EC cells 124 each adapted to store an EC bit. Thus memory 120 comprises data cells 122A through 122N and EC cells 124A through 124N.
When data is written to memory 106, an EC input circuit 108 generates EC bits based on the data bits using an algorithm such as the Hamming code, writes the data bits to the data cells 122 of a memory line 120 in memory 106, and writes the EC bits to the EC cells 124 of that memory line 120. When data is read from memory 106, an EC output circuit 110 processes the data.
EC output circuit 110 comprises an error correction circuit 116 and an optional error detection circuit 118. Error correction circuit 116 uses the EC bits read from a memory line 120 to correct errors in the data bits read from the memory line 120. Optional error detection circuit 118 indicates whether the data bits contain errors that were detected but not corrected.
ICs such as IC 102 are tested by writing data to the memory 106, reading the data from the memory 106, and comparing the read and written data. While this approach is sufficient to detect most flaws in the data cells 122, it cannot detect any flaws in the EC cells 124.